(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a self-aligned dual damascene structure.
(2) Description of the Prior Art
The manufacturing of semiconductor devices requires the application of multiple diverse technical disciplines that collectively enable the continuing advancements of device performance that has been accomplished ever since the initiation of the semiconductor device. These various disciplines address various aspects of the device creation whereby typically a plurality of active circuits is created in a semiconductor substrate. To create a collection of circuits, commonly referred to as Integrated Circuits (IC's), the individual circuits are interconnected with metal leads. To further increase device density, multiple layers of interconnect metal can be created. These multiole layers of interconnect metal are separated by layers of dielectric or by insulating layers. Adjacent layers of metal lines are interconnected by means of metal contact plugs or vias.
The semiconductor industry has, over the last several decades, been driven by a continued striving to improve device performance, which requires a continued decrease of semiconductor device feature size. In present day semiconductor devices, it is not uncommon to encounter feature size in the deep sub-micron range. With this decrease in device feature size, sub-micron metal interconnects become increasingly more important. A number of different approaches are used in the art for the formation of patterns of interconnect lines, most of these approaches start with the deposition of a patterned layer of dielectric where the pattern in the dielectric forms contact openings between overlying metal and underlying points of electrical contact. A layer of metal is deposited over the layer of dielectric and patterned in accordance with the required pattern of interconnect lines whereby the interconnect lines, where required, align with the underlying contact openings. The patterning of the layer of metal requires the deposition of a layer of photoresist over the layer of metal, the photoresist is exposed typically using photolithographic techniques and etched, typically using a dry etch process. The patterned layer of photoresist is removed after the interconnect metal line pattern has been created leaving the interconnect line pattern in place. For sub-micron metal line sizes, these highlighted processing steps encounter a number of problems that are typical of device sub-miniaturization. These problems are problems of poor step coverage of the deposited metal (the metal should be evenly deposited and should fill the profile for the metal line with equal metal density), problems of etching (using dry etching but metal such as copper and gold are difficult to plasma etch) and problems of step coverage and planarization for the overlying layer of dielectric.
In the formation of semiconductor integrated circuits, it is common practice to form interconnect metal line structures on a number of different levels within the structure and interconnecting the various levels of wiring with contact or via openings. The first or lowest level of interconnect wires is typically formed as a first step in the process after which a second or overlying level of interconnect wires is deposited over the first level. The first level of interconnect wires is typically in contact with active regions in a semiconductor substrate but is not limited to such contacts. The first level of interconnect can for instance also be in contact with a conductor that leads to other devices that form part of a larger, multi-chip structure. The two levels of metal wires are connected by openings between the two layers, these openings are filled with metal whereby the openings between the two metal layers are lined up with and match contact points in one or both of the levels of metal lines.
The brief description of the process of metalization that has been given above has been described with reference to the damascene and dual damascene processes which form two widely used approaches in creating metal interconnects. The application of the Damascene process continues to gain wider acceptance, most notably in the process of copper metalization due to the difficulty of copper dry etch where the damascene plug penetrates deep in very small, sub-half micron, Ultra Large Scale Integrated (ULSI) devices. Recent applications have successfully used copper as a conducting metal line, most notably in the construct of CMOS 6-layer copper metal devices.
With increasing device densities, the area that is available for circuit wiring becomes relatively more important as a potential limiting factor in device performance. This has led to the development of multi-layer wiring where the dual damascene structure has found wide use.
For the creation of the single damascene structure, vias only are created. For the creation of the dual damascene, vias are created and conductors are created above the vias. For the dual damascene, special etch procedures can be used to form both the vias and the conductor patterns in the dielectric layer before the deposition of metal and the metal CMP. A thin etch stop layer can be used for this purpose between two layers of dielectric SiO.sub.2.
With the damascene process a metal via plug is first formed in a surface, typically the surface of a semi-conductor substrate. A layer of dielectric (for instance SiO.sub.2) is deposited over the surface (using for instance PECVD technology); trenches (for metal lines) are formed in the dielectric (using for instance RIE technology). Metal is deposited to fill the trenches; the excess metal on the surface is removed. A planar structure of interconnect lines with metal inlays in the (intra-level) dielectric is achieved in this manner.
For the dual damascene process, the processing steps can follow three approaches.
Approach 1, the via is created first. The vias are formed by resist patterning after which an etch through the triple layer dielectric stack is performed. This is followed by patterning the conductor in the top layer of SiO.sub.2 thereby using the SiN as an etch stop layer.
Approach 2. The conductor first process. The conductor patterns is formed by resist patterning and by etching the conductor patterns into the first SiO.sub.2 layer thereby using the SiN layer as an etch stop layer. This is followed by via resist patterning and etching through the thin layer of SiN and the second SiO.sub.2 layer.
Approach 3. Etch stop layer first. The first SiO.sub.2 layer is deposited, followed by the thin layer of SiN as etch stop, followed by the via resist patterning and etching of the SiN layer. This is followed by depositing the top SiO.sub.2 layer and then the conductor patterning. In etching the conductor pattern in the top SiO.sub.2 layer, the etching process will be stopped by the SiN layer except where the via holes are already opened in the SiN layer thereby completing the via holes etching in the first SiO.sub.2 layer simultaneously.
FIGS. 1a and 1b further detail the above.
FIG. 1a gives and overview of the sequence of steps required of forming a Prior Art dual Damascene structure. The numbers referred to in the following description of the formation of the dual Damascene structure relate to the cross section of the completed dual Damascene structure that is shown in FIG. 1b.
FIG. 1a, 21 shows the creation of the bottom part of the dual Damascene structure by forming a via pattern 22 on a surface 24, this surface 24 can be a semiconductor wafer but is not limited to such. The via pattern 22 is created in the plane of a dielectric layer 20 and forms the lower part of the dual Damascene structure. SiO.sub.2 can be used for this dielectric.
FIG. 1a, 22 shows the deposition within plane 30 (FIG. 1b) of a layer of non-metallic material such as poly-silicon on top of the first dielectric 20 and across the vias 22, filling the via openings 22.
FIG. 1a, 23 shows the formation of the top section 41 of the dual Damascene structure by forming a pattern 41 within the plane of the non-metallic layer 30. This pattern 41 mates with the pattern of the previously formed vias 22 (FIG. 1a, 21) but it will he noted that the cross section of the pattern openings 41 within the plane 30 of the non-metallic layer is considerably larger than the cross section of the via openings 22 (FIG. 1a, 21). After pattern 41 has been created and as part of this pattern creation step, the remainder of the non-metallic layer 30 is removed, the pattern 41 remains at this time.
FIG. 1a, 24 shows the deposition and planarization (down to the top surface of pattern 41) of an intra level dielectric (ILD) 50, a poly-silicon can be used for this dielectric.
FIG. 1a, 25 shows the creation of an opening by removing the poly-silicon from the pattern 41 and the vias 22. It is apparent that this opening now has the shape of a T and that the sidewalls of the opening are not straight but show a top section that is larger than the bottom section.
FIG. 1a, 26 shows the cross-section of the dual damascene structure where a barrier 70 has been formed on the sides of the created opening. The opening, which has previously been created by removing the poly-silicon from the pattern 41 and the vias 22, has been filled with a metal. Metal such as Wolfram or copper can be used for this latter processing step.
U.S. Pat. No. 5,543,253 highlights another Prior Art method of forming a T-shaped gate structure, in this case using electron beam lithography. This method will be briefly highlighted her for completeness and with reference to FIG. 2. The process starts with the deposition of two layers of positive photoresist, a lower layer 12 of PMMA resist and a upper layer 14 of MMA resist, over the surface of a substrate 10, see FIG. 2a. The two layers of photoresist are exposed (16, FIG. 2a) by an electron beam in a predetermined pattern. The two layers of photoresist are developed and removed in accordance with the pattern of e-beam exposure, see FIG. 2b. The sensitivity of the two layers of photoresist to the e-beam exposure is selected such that the opening that is created resembles essentially the opening of a dual damascene structure. By blanket depositing a layer 20 (FIG. 2c) of metal over the surface of the upper layer 14 of photoresist and the bottom (18) of the created dual damascene opening and by subsequently removing the resist patterns 12 and 14 together with the layer 20 of deposited metal, the T-shaped dual damascene structure as shown in FIG. 2e is created. This method presents a number of problems such as being time consuming due to the relatively slow e-beam exposure process, diffusion of the deposited metal into the underlying layers of photoresist due to the high temperatures that are required for the metal deposition process and difficulties experienced in integrating an e-beam lithography process with the more conventional optical steppers that are typically used for other device processing steps within a device manufacturing environment.
The invention addresses the above indicated problems of dual damascene creation in addition to the problem of relatively increased parasitic gate resistance that occurs due to shrinking device dimensions for the conventional gate structure. This increased parasitic device resistance can rapidly decrease the device high-speed performance. For the conventional titanium silicide process that is applied in the creation of T-shaped gates to establish electrical contacts, the TiSi.sub.2 that is used for the silicide creation must readily transfer from the high-resistance C49 structure to the (low resistance) C54 structure, even in an environment where the created silicide line width is below grain size. This problem is also addressed by the invention while the invention further prevents the agglomeration (the action or process of collecting in a mass) of silicide grains. This agglomeration is particularly prone to occur during subsequent processing steps of (high temperature) anneal.
U.S. Pat. No. 5,543,253 (Park et al.) teaches a method for a T-shaped gate using Dual damascene photoresist lift off process. Overall, this patent is close to the invention.
U.S. Pat. No. 5,689,140 (Shoda) discloses a modified dual damascene process to form contacts.
U.S. Pat. No. 5,614,765 (Avanzino et al.) teaches a dual damascene process.
U.S. Pat. No. 5,498,560 (Sharma et al.) discloses a self-aligned T-shaped gate process.